OnTime PTP and gPTP IP

The OnTime IEEE 1588 Std 2008 (PTP) protocol stack for Grand Master-, Transparent-, Ordinary- and Slave only Clock operation or IEEE 802.1as gPTP (AVB) for Ordinary Clock, time-aware-bridge or Slave Clock only contain two parts:

• TSM, Time Synchronization Module
• Protocol Software

The TSM performs low level time stamping of PTP events packets and also contains a high resolution clock.  The TSM is implemented in VHDL or Verilog.

The PTP Transparent Clock is fully implemented in the TSM.

The Protocol Software contains support for PTP Grand Master-, Ordinary- or Slave Clock or gPTP Ordinary Clock, time-aware-bridge or Slave Clock. 

The OnTime time synchronization module (TSM) is a flexible hardware implementation supporting the PTPv2 standard (IEEE Std 1588™ 2008).  The TSM is vendor-independent and suitable for integration on any FPGA or ASIC platform. Source code is available both in VHDL and Verilog.

The Protocol Software van also by used with MACs from other vendors with PTP or gPTP support.

TSM features

1-step and 2-step Peer-to-Peer (P2P)/ End-to End (E2E) Transparent Clock in hardware Full PTP wire speed performance is possible General purpose inputs for event triggering Two frequency outputs VHDL/Verilog source code Ethernet CPU interface PTP unicast support 10/100/1000MII/GMII interfaces PTP multicast filtering of DELAY_REQ packets Scalable port count PTP software protocol stack available Customization according to customer needs Compliance to the 802.1as (gPTP) Prepared for the PTP telecom profile

 

Implementation options

The TSM can be integrated in a PHY or in MAC. In a multiple port environment, a transparent clock can be implemented fully in hardware if desirable.

Time stamp database

Ingress event packets are time stamped in hardware by the ingress packet receiver (IPR). The time stamps are stored in a common database together with packet identifiers. A CPU running the PTP software stack can read out the database content by communicating with the TSM via Ethernet. Configuration and other TSM communication are done via Ethernet. No other interface is needed for communication between the TSM and a CPU.

Hardware Transparent clock

The 1-step hardware transparent clock is not dependent of CPU support making it suitable for unmanaged solutions. The 1-step hardware transparent clock implementation supports both 1-step and 2-step master- and slave clocks. The Egress Packet Transmitter (EPT) will perform residence time calculation, update correction fields and compute relevant checksums before the PTP packet is forwarded on an egress port. The Transparent Clock is also be independent of the PTP load since TSM can handle full PTP wire speed if the TSM is configured with a sufficient data base depth.

General purpose I/O

Time stamping of external inputs is easy. Ethernet frames can be sent upon trigger or timestamps can be stored in the database. Two configurable frequency outputs are available.

Protocol Software

A software application that interfaces the TSM can also be provided from OnTime. This application contains support for PTP Grand Master-, Ordinary- or Slave Clock operation with E2E or P2P support, TSM configuration and TSM clock control. The Protocol Software is written in standard C with minimum OS and CPU dependency. Porting to different operating systems is easy since the only TSM interface is based on IPv4 UDP/IP sockets.

---

Please contact OnTime Networks if you are interested in this IP and customization and integration on your hardware.